Projects
Microservers and System Software
I am leading the Microserver Architectures and System Software team at the Barcelona Supercomputing Center.
Research projects
EuroEXA is a €20M project, which starts in September 2017 and is funded by the European Commission's FETHPC-01-2016 call. The project has the ultimate goal of achieving world-class extreme scale capabilities in HPC platforms, technologies and applications. EuroEXA will co-design a balanced HPC architecture for compute- and data-intensive applications using a cost-efficient modular integration approach, demonstrated using key HPC applications from climate/weather, physics/energy and life-science/bioinformatics. I am the project's Applications and Systems Software Technical Manager, with overall responsibility for the system software (operating system, resource management, parallel filesystem, and run-time systems) and applications (14 production applications from major institutions across Europe, including ECMWF, STFC, BSC, FHG, IMEG, INFN and INAF). I will drive the co-design process in close collaboration with the project's Hardware Technical Manager, as well as the entire project consortium. I am also Leader of WP2 Applications, co-design, porting and evaluation. I am also the project's Principal Investigator at BSC.
BSC Principal Investigator (PI), and leader of WP3 Enablement of Software Compute Node (total 242 PMs). Leader of task to develop OmpSs task-based programming model to address the issues related with building exascale systems from low-power components, including supporting the ExaNode UNIMEM architecture in SMP OmpSs, Cluster OmpSs and hybrid MPI+OmpSs.
Principal Investigator (PI) of EUROSERVER at BSC. Director of two PhD students: (a) hypervisor support for programming models and (b) interconnect topology and energy proportionality, which led to publications at LCN 2015 (Exploring Interconnect Energy Savings Under East-West Traffic Pattern of MapReduce Clusters) and LCN 2016 (Controlling Network Latency in Mixed Hadoop Clusters: Do We Need Active Queue Management?). An overview of the EUROSERVER project is available: EUROSERVER: Share-Anything Scale-Out Micro-Server Design (DATE2016).
PhD co-advisor of Karthikeyan Saravanan, on thesis Performance-aware Energy Optimizations in Networks for HPC, regarding interconnect energy proportionality, to be defended by the end of 2016. This thesis develops the PerfBound technique for managing Energy Efficient Ethernet (EEE) to minimise the interconnect energy consumption of HPC workloads, subject to a bound on the performance overheads (A Performance Perspective on Energy Efficient HPC Links, ICS14). The thesis also analyses the energy–performance tradeoff for EEE (Power/Performance evaluation of Energy Efficient Ethernet (EEE) for High Performance Computing, ISPASS 2013 and Exploring Multiple Sleep Modes in On/Off based Energy Efficient HPC Networks, ICCD 2015).
Leading engineer analysing the performance of data centre applications on the Mont-Blanc prototype system. Presented invited talks at IS-ENES 2014, RIKEN AICS 2013, EU Workshop on strategic directions for next-generation computing 2013, ISCA 2013, LEAP 2013 (video below), DATE 2013, IS-ENES 2013, and BUX 2012 (Warwick, UK). The Mont-Blanc project has been influential in generating interest in High-Performance Computing (HPC) using embedded System-on-Chips (SoCs), a philosophy developed in the SC13 paper, Supercomputing with Commodity CPUs: Are Mobile SoCs Ready for HPC?
The ACOTES project worked to increase programmer productivity in the area of streaming applications, through advances in programming model and compiler technology. The programming model introduced C annotations to define the streaming semantics. A source-to-source compiler supported high-level transformations controlled by the partitioning algorithm. The translated program used the Nanos++ runtime system. The project also included work on vectorisation in the GCC backend. My PhD studies were performed in the context of ACOTES: abstract model of streaming program and target hardware (Abstract Streaming Machine), static partitioning algorithm and static buffer sizing algorithm for the prototype ACOTES compiler. I also developed Starsscheck, a tool (based on Valgrind) to check the correctness of OmpSs (formerly StarSs) annotations. The project as a whole is described in the IJPP journal publication, ACOTES Project: Advanced Compiler Technologies for Embedded Streaming.
Extreme Value Theory
Extreme Value Theory (EVT) is an important branch of statistics, which has found multiple applications in civil engineering, material testing, finance and risk management. It provides powerful theorems and tools, but its application in computer science and engineering has so far been marginal. I am co-author on two papers applying Extreme Value Theory (EVT) to computer science: Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem, published in MICRO 2012, and Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach, IEEE Transactions on Computers (impact factor 1.659) Featured Paper of the Month (1 of 28 papers published).
Research strategy
Co-chair of Working Group on Programming Models in the European Technology Platform for High Performance Computing (ETP4HPC), the main organisation that represents the whole HPC industry and academia within Europe (now 64 members: companies, SMEs and research centres). I am co-leader of the Working Group on Programming Environment for the ETP4HPC SRA, held since 2012 and an author of the ETP4HPC Strategic Research Agenda.
EuroLab-4-HPC is a two-year Horizon 2020 project to build the foundation for a European Research Centre of Excellence in High-Performance Computing (HPC) systems. The main objectives are to (a) join HPC system research groups around a long-term HPC research agenda, by forming an HPC research roadmap and joining forces behind it, (b) define an HPC curriculum to foster future European technology leaders, (c) accelerate commercial uptake of new HPC technologies, (d) build an HPC ecosystem of researchers, system providers, VCs etc., and (e) form a business model for the EuroLab-4-HPC excellence centre.
I am leader of WP2 Research, which (i) sets a long-term vision for excellence in European academic HPC research, (ii) coordinates efforts to build common research platforms, including multi-disciplinary workshops to address cross-cutting issues and short research stays, and (iii) identifies seeds for innovation and exploitation, as well as mentoring and monitoring of the research projects to accelerate innovations in HPC. Leader of Working Group 2: System Software and Programming Environment and Working Group 4: HPC Applications.
The objective of the RETHINK big Project is to bring together the key European hardware, networking, and system architects with the key producers and consumers of Big Data to identify the industry coordination points that will maximize European competitiveness in the processing and analysis of Big Data over the next ten years
Rethink Big: member of Editorial Team, editor for section on Node Architecture, and key role in BSC's coordination of the project. Please take a look at the Rethink Big Roadmap.
HiPEAC is a European Network of Excellence (NoE) with the mission to steer and increase European research in the area of high-performance and embedded computing systems. “The HiPEAC network, since its creation in 2004, triggered fundamental changes in the European computing systems community, and it has created a long lasting impact in Europe” (EU Project Officer Panagiotis Tsarchopoulos). The network stimulates cooperation between a) academia and industry and b) computer architects and tool builders. HiPEAC has 430 members from 275 institutions in 37 countries.
I handled the task to analyse options for self-sustainability of the HiPEAC Network of Excellence, beyond the end of the EU Network of Excellence instrument. This task required an analysis of comparable research organisations, projections of income versus ongoing expenses, and legal, financial and organisational structure. I was also the proofreader for HIPEACinfo quarterly newsletter, which is sent to more than 500 researchers and company managers from academia and industry, in Europe, America and Asia.
Industrial projects
I was a core member of the multi-disciplinary team that designed the NEON / Advanced SIMD SIMD ISA, which is now a key part of the ARM architecture and mandatory in ARMv8-A. Advanced SIMD was first introduced in ARM Cortex-A8, in 2005, and the design has changed little as of 2016. It is implemented in almost 50% of all mobile phones worldwide. I am principal researcher and first author on 3 international granted patents. I was also technical lead for the MP3 decoder, Microsoft WMA decoder, MPEG-4 video encoder and decoder, and Dolby digital decoder.
From 1991 to 1993 I developed Phaethon for Acorn Archimedes. This was initially a personal project, but an early version of the game was discovered by The Serial Port Ltd, and it was launched commercially in December 1993 under the System Interrupt label. Phaethon received positive reviews ("If System Interrupt is going to keep up this standard with future releases, it is soon going to become established as one of the top entertainment labels for Acorn machines", Archimedes World, Jan 1994; "The motion is smooth, fast, and very polished", Acorn Computing, Dec 1993). It is now freely available from Acorn Arcade. The game was implemented in 17,684 lines of assembler, and it features texture mapped graphics and triple buffering, techniques that were innovative at the time. Part of the source code is available here. I published six other small programs as open source in magazines between 1988 and 1992.